1. Field of the Invention
The present invention relates to a flip-chip bonding technique for mounting an optical device on a PLC (Planar Lightwave Circuit), and more particularly to a flip-chip bonding structure and method for improving the degree of the vertical alignment of an optical device relative to a PLC.
2. Description of the Related Art
Generally, the flip-chip bonding technique is one of various methods of bonding a semiconductor device onto a substrate. Different from the conventional wire-bonding or soldering method, in the flip-chip bonding method an array of metal pads are first formed on the surfaces of both the semiconductor device to be bonded and the substrate. Then, solder bumps are placed on either the metal pads of the substrate or the metal pads of the semiconductor device, or both. The semiconductor device is mounted in an upside-down manner over the substrate so that the metal pads or the solder bumps of the semiconductor device are aligned with the corresponding metal pads or the solder bumps of the substrate. Thereafter, solder material of the solder bumps is heated and re-flowed to physically bond the semiconductor device to the substrate.
As the optical characteristics of the optical device are sensitive to the vertical alignment of the optical device relative to the substrate, a small error in the vertical alignment drastically deteriorates the optical characteristics of the optical device. Therefore, in order to connect the optical device to an optical waveguide, such as the PLC, a precise vertical alignment of the optical device relative to the optical waveguide is required. In order to align the optical device, such as a laser diode with the optical waveguide, a degree of precision of tolerance of less than ±1 μm is usually required.
FIG. 1 is a cross-sectional view of a conventional flip-chip bonding structure between an optical device and a PLC. As shown in FIG. 1, the PLC (Planar Lightwave Circuit) 10 comprises a silicon substrate 11, a lower clad layer 12, a core 13, and an upper clad layer 14. Furthermore, the PLC 10 comprises a metal electrode 15 and a solder bump 16. The metal electrode 15 and the solder bump 16 are deposited successively on an etched surface of a designated area of the PLC 10 for mounting the optical device 20. The designated area of the PLC 10 for mounting the optical device 20 is etched by a deep-etching method. Then, the optical device 20 provided with solder pads is bonded to the PLC 10 by the flip-chip bonding method using the surface tension of the solder bump 16 of the PLC 10. That is, after aligning the solder pad of the optical device 20 relative to the corresponding solder bump 16 located on the PLC 10, the optical device 20 and the PLC 10 are heated so as to re-flow the solder bump 16. As the solder bump 16 of the PLC 10 is re-flowed, the solder bump 16 assumes its most stable shape. The re-flowed solder bump 16 forms a bond between the optical device 20 and the PLC 10.
However, in the aforementioned prior art, the depth of the etched area of the PLC 10 from the upper-clad layer 14 to the lower-clad layer 12 is approximately 30 μm. Therefore, it is difficult to adjust precisely the depth of the etched area of the PLC 10 within a range of the required tolerance in the optical device 20. In addition, some error occurs in the thickness of the solder bump 16 formed by depositing a metal, which in turn deteriorates the optical characteristics. Furthermore, in the flip-chip bonding method, as the solder bumps of the PLC are re-flowed at high temperature and the optical device is bonded to the re-flowed solder bumps of the PLC, errors in the vertical alignment of the optical device relative to the PLC occur according to the bonding pressure and the re-flowing temperature, thereby seriously deteriorating the optical characteristics of the optical device further.